1. Field of the Invention
The invention relates to a refresh operation in a synchronous semiconductor memory device, and more particularly to a synchronous semiconductor memory device, enabling reduction of current consumption in a self-refresh operation.
2. Description of Related Art
With the recent development in computer technology which realizes animations and other advanced features, there is a growing demand for increasing the capacity and speed of semiconductor memory devices represented by a dynamic random access memory (DRAM). To meet this demand, synchronous semiconductor memory devices, represented by a large-capacity synchronous DRAM, have been developed. On the other hand, this demand necessarily results in an increase in current consumption in a circuit operation, so that it is desired to reduce current consumption in a synchronous semiconductor memory device.
Particularly, a refresh operation of memory cells in a memory device such as a synchronous DRAM needs to be performed in a predetermined cycle. Therefore, current consumption in a refresh operation have been reduced by setting the refresh cycle long in accordance with the actual performance value of charge retention time determined based on charge retention characteristics.
In addition, since a synchronous semiconductor memory device operates in synchronization with an external basic clock, device temperature rises as operating current is increased due to an increase in the speed of the external basic clock. Because charge retention characteristics of memory cells largely depend on the device temperature, charge retention time is decreased as the temperature rises. Therefore, it is necessary to shorten the refresh cycle in a high temperature range, and to set the refresh cycle suitable for the device temperature which changes according to the frequency of the external basic clock.
With regard to conventional arts, for example, the Japanese Laid-Open Patent Publication No.5-217369 describes a refresh timer that outputs a refresh signal in a semiconductor memory device requiring a refresh operation of memory cells, comprising oscillation circuit for outputting an oscillation signal of predetermined frequency, frequency division circuit for dividing frequency of the oscillation signal, and adjustment circuit for adjusting the frequency division cycle of the frequency division circuit to the value suitable as the refresh cycle of the memory cells.
In the aforementioned refresh timer in the semiconductor memory device, the refresh cycle can be adjusted to the accurate refresh cycle required for each device after production, even when oscillation circuit with relatively poor accuracy is used.
The Japanese Laid-Open Patent Publication No.5-307883 discloses an oscillator circuit, comprising inverter circuits between a high-potential power line and a low-potential power line in which predetermined number of PMOS transistors and NMOS transistors are connected in series; first resistance circuit between the high-potential power line and the low-potential power line in which a first PMOS transistor for inputting to gates the potential level of the low-potential power source line and a resistor are sequentially connected in series, and a contact between the first PMOS transistor and the resistor is a low-potential output end; and second resistance circuit between the high-potential power source line and the low-potential power line in which a resistor and a first NMOS transistor for inputting to gates the potential level of the high-potential power source line are sequentially connected in series, and a contact between the resistor and the first NMOS transistor is an high-potential output end, wherein the low-potential output end of the first resistance circuit is connected with the gates of the PMOS transistors in the inverter circuits proximate to the high-potential power source line, and the high-potential output end of the second resistance circuit is connected with the gates of the NMOS transistors in the inverter circuits proximate to the low-potential power source line, and the inverter circuits are multi-stage connected in a loop-shape to generate a predetermined clock cycle.
Since the charge retention time of memory cells in a semiconductor memory device is decreased as the device temperature rises, the temperature characteristics of the refresh cycle should be set to have a negative correlation to the device temperature in order to retain charge. In view of this, in the aforementioned oscillator circuit, the temperature characteristics of the oscillation cycle are set to have the negative correlation to the device temperature just as the temperature characteristics of the refresh cycle for retaining charge, and thus the refresh cycle is shortened as the device temperature rises. In this way, the reliability with which the memory cells retain charge at high temperatures is enhanced. In addition, since the refresh cycle can be set long at normal working temperatures, the operating current for a refresh operation can be prevented from increasing. Accordingly, current consumption can be reduced.
Furthermore, the Japanese Laid-Open Patent Publication No.7-73668 describes a self-refresh cycle adjustment circuit in a semiconductor memory device which generates a master clock signal for setting the refresh cycle in a semiconductor memory device. This self-refresh cycle adjustment circuit comprises pulse train generation circuit for generating pulse trains in a predetermined cycle according to the refresh mode set by an external control signal, and dividing frequency of the pulse trains sequentially to output a number of frequency-divided pulse trains each of which has a different cycle; at least one temperature detection circuit for detecting change in surrounding temperature based on the internally-set standard level to output a temperature detection signal; and master clock generation circuit for selecting one of the frequency-divided pulse trains according to the temperature detection signal and outputting a master clock signal based on the selected frequency-divided pulse train.
In the aforementioned self-refresh cycle adjustment circuit, the self-refresh cycle can be actively adjusted according to change in surrounding temperature. Furthermore, the self-refresh cycle can be automatically adjusted so as to be adapted to various operating environments.
In the refresh timer described in the Japanese Laid-Open Patent Publication No.5-217369, the refresh cycle can be accurately adjusted to the refresh cycle required for each semiconductor memory device after production, even when oscillation circuit with relatively poor accuracy is used.
However, this adjustment needs to be made to each semiconductor memory device using adjustment circuit such as a trimming circuit, and the optimum refresh cycle cannot be determined without measuring variations in characteristics of each device due to production variations. Since characteristics to be measured include temperature characteristics, much test time is required to measure characteristics before adjustment, resulting in a problem that productivity of semiconductor devices cannot be improved.
Furthermore, when the refresh cycle is adjusted using adjustment circuit such as a trimming circuit, a refresh operation is always performed in a constant cycle. Since this cycle needs to be set such that the memory cells can retain charge even under the most extreme conditions (for example, when power supply voltage is low, or temperature is high), a refresh operation is performed in a cycle shorter than that required based on charge retention characteristics of the memory cells under normal use conditions. This causes the problem that current consumption in a refresh operation becomes greater than necessary.
In the oscillator circuit disclosed in the Japanese Laid-Open Patent Publication No.5-307883, the self-refresh cycle is shortened as temperature rises to enhance the reliability with which the memory cells retain charge at high temperatures. At the same time, the self-refresh cycle is set long at normal working temperatures so as to reduce current consumption. In the self-refresh cycle adjustment circuit described in the Japanese Laid-Open Patent Publication No.7-73668, the self-refresh cycle can be actively adjusted according to change in surrounding temperature.
However, due to production variations, there are variations in temperature characteristics of charge retention in memory cells, correlation characteristics of the self-refresh cycle to temperature in the oscillator circuit described in the Japanese Laid-Open Patent Publication No.5-307883, or detection characteristics of the temperature detection circuit described in the Japanese Laid-Open Patent Publication No.7-73668, and the variations in these characteristics are distributed within a predetermined range. The operating constant of the oscillator circuit or the temperature detection circuit needs to be set based on the worst condition, that is, the limit of the distribution range. Therefore, if production requirements are loosened to admit a wide distribution range of variations in characteristics, a refresh operation is performed in a refresh cycle shorter than that required based on the characteristics of a unit in the center of the distribution range. This causes the problem that current consumption in a refresh operation becomes greater than necessary. If the admissible distribution range of variations in characteristics is limited, load of production becomes great to keep variations in characteristics within the admissible distribution range, though current consumption reduction in a refresh operation can be realized.
Accordingly, it is an object of the invention to overcome the aforementioned problems of the conventional arts by providing a synchronous semiconductor memory device which provides the refresh cycle optimum for charge retention characteristics without being influenced by production variations, and without requiring much test time to measure characteristics before adjustment of the refresh time, and reduces current consumption in a refresh operation.
To achieve the aforementioned object, a synchronous semiconductor memory device requiring a refresh operation according to one aspect of the invention is configured so as to comprise detection circuit for detecting the frequency of an external basic clock, and cycle control circuit for controlling the refresh cycle based on a frequency detection signal from the detection circuit.
In the aforementioned synchronous semiconductor memory device, as shown in a diagram illustrating a first principle in FIG. 1, frequency detection circuit 1 receives an external basic clock CLK and outputs a frequency detection signal A according to the frequency of the external basic clock CLK. The frequency detection signal A is input to refresh cycle control circuit 2, which outputs a refresh signal OSC having the refresh cycle controlled based on the frequency detection signal A.
In addition, a refresh method of the synchronous semiconductor memory device requiring periodical refresh of memory cells according to another aspect of the invention comprises a detection process of detecting the frequency of an external basic clock and a cycle control process of controlling a refresh cycle based on a frequency detection signal from the detection process.
In the refresh method of the aforementioned synchronous semiconductor memory device, an external basic clock is received and a frequency detection signal responsive to the frequency of the external basic clock is output during the frequency detection process. The frequency detection signal is received and a refresh signal OSC having the refresh cycle controlled based on the frequency detection signal is output during the refresh cycle control process.
In this way, in the synchronous semiconductor memory device, the refresh cycle is set in accordance with the charge retention characteristics at each device temperature which changes according to the frequency of the external basic clock CLK. Therefore, it is not necessary to perform a test to measure temperature characteristics of charge retention in memory cells to set the refresh cycle for each synchronous semiconductor memory device.
In addition, it is not required to use temperature detection circuit whose accuracy is difficult to ensure due to production variations, and it is possible to use a stable signal, an external basic clock as a temperature sensor. Thus, the refresh cycle suitable for device temperature can be set easily without fail over, that is, the optimum refresh cycle can be realized over a full device temperature range, enabling reduction of current consumption.
The above and further objects and novel features of the invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are purpose of illustration only and not intended as a definition of the limits of the invention.